1. Field of the Invention
The present invention generally relates to semiconductor devices and to the fabrication thereof, and more particularly, the present invention relates to semiconductor devices utilizing stress memorization, and to methods of fabricating the same.
2. Description of the Related Art
Transistor devices have been reduced in size to the extent where scaling limitations (e.g., gate oxide leakage and short channel effects) are becoming a significant roadblock to further device integration. The consensus in the art is that improvements in “channel mobility” can largely overcome or reduce the adverse effects these scaling limitations. Channel mobility generally refers to the ease with which electrons (for NMOS devices) and holes (for PMOS devices) are capable of being transferred within the channel region of the transistor device.
One technique being explored to enhance channel mobility is to induce strain within the channel region to thereby physically elongate or compress atomic bonds. In particular, tensile stress within the channel region of an NMOS device has been found to improve electron mobility in the channel, while compressive stress within the channel region of a PMOS device can improve hole mobility within the channel.
“Stress memorization” (SM) is one technique that may be utilized to induce tensile stress within the channel region of an NMOS device. Here, an SM layer is deposited over the gate structure of the NMOS device. The SM layer is generally formed of an insulating material, such as SiN. During a subsequent anneal, tensile stresses induced in the SM layer cause compressive stresses in the gate electrode and in the adjacent source and drain regions. These compressive stresses cause tensile stress to be induced in the channel region of the NMOS device. These stresses are “memorized” during the anneal process, and the SM layer is then removed.
However, the channel region tensile stress induced by the SM layer can adversely impact the operating performance of an adjacent PMOS device. Accordingly, the SM layer must be patterned to remove the portion thereof overlying the PMOS device prior to the anneal process. This requires execution of additional masking and etching processes, thus increasing costs and fabrication times.
In the meantime, one technique utilized to induce compressive stress within a PMOS device is to epitaxially grow SiGe source/drain regions on opposite sides of the channel region. The SiGe epitaxial regions have a larger lattice constant than that of the intervening channel region. The resultant tensile stress in the epitaxial regions induces a compressive stress in the channel region of the PMOS region. Hole mobility in the channel therefore increases, which in turn enhances the operating speed of the PMOS transistor.
Again, however, in order to avoid degradation in the performance of the PMOS transistor, it is necessary to perform the costly and time consuming steps associated with patterning the SM layer to remove the same from over the PMOS device prior to annealing the SM layer to induce tensile stress the NMOS channel.